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introduction three different configurations that an l6561-based flyback converter can assume have been identified. they are illustrated in fig. 1. configurations a) and b) are basically conventional flyback converters. the former works in tm (transi- tion mode, i.e. on the boundary between continuous and discontinuous inductor current mode), therefore at a frequency depending on both input voltage and output current. the latter works at a fixed frequency, imposed by the synchronisation signal, and is there- fore completely equivalent to a flyback converter based on a standard pwm controller. configuration c), which most exploits the aptitude of the l6561 for performing power factor correction, works in tm too but quite differently: the input ca- pacitance is so small that the input voltage is very close to a rectified sinusoid. besides, the control loop has a narrow bandwidth so as to be little sensitive to the twice mains frequency ripple appearing at the output. march 2000 ? AN1059 application note design equations of high-power-factor flyback converters based on the l6561 by claudio adragna despite specific for power factor correction circuits using boost topology, the l6561 can be suc- cessfully used to control flyback converters. among the various configurations that an l6561-based flyback converter can assume, the high-pf one is particularly interesting because of both its peculiar- ity and the advantages it is able to offer. ac-dc adapters for mobile or office equipment, off-line bat- tery chargers and low-power smps are the most noticeable examples of application that this configu- ration can fit. this paper describes the equations governing such a kind of flyback converter with the aim of provid- ing a number of relationships useful to the system designer. vcc zcd gd l6561 vac c bulk opto + tl431 vout disable figure 1a. tm flyback configuration vcc zcd gd l6561 vac c b ulk opto + tl431 synch vout disable figure 1b. synchronised flyback configuration vcc zcd gd l6561 vac c in inv opto + tl431 (b w <100 hz) vout comp disable mult figure 1c. high-pf flyback configuration 1/20
actually, the high power factor (pf) exhibited by this topology can be considered just as an additional benefit but not the main reason that makes this solution attractive. in fact, despite a pf greater than 0.9 can be easily achieved, it is a real challenge to comply with emc norms regarding the thd of line cur- rent, especially in universal mains applications. there are, however, several applications in the low-power range (to which emc norms do not apply) that can benefit from the advantages offered by a high-pf flyback converter. these advantages can be sum- marised as follows: l for a given power rating, the input capacitance can be 200 times less, thus the bulky and costly high voltage electrolytic capacitor after the rectifier bridge will be replaced by a small-size, cheaper film ca- pacitor. l efficiency is high at heavy load, more than 90% is achievable: tm operation ensures low turn-on losses in the mosfet and the high pf reduces dissipation in the rectifier bridge. this, in turn, mini- mises requirements on heatsinks; l low parts count, which helps reduce encumbrance and assembly cost. in addition, the unique features of the l6561 offer remarkable advantages in numerous applications: l efficiency is high even at very light load: the low current consumption of the l6561 minimises the power dissipated by both the start-up resistor and the self-supply circuit. an l6561-based high-pf fly- back converter can easily meet blue angel regulations; l additional functions available: the l6561 provides overvoltage protection as well as the possibility to enable/disablethe converter by means of its zcd pin. there are, on the other hand, some drawbacks, inherent in high-pf topologies, limiting the applications that such a converter can fit (ac-dc adaptors, battery chargers, low-power smps, etc.) and which one has to be aware of: l twice-mains-frequency ripple on the output: unavoidable if a high pf is desired. a large output ca- pacitance will reduce its amount. speeding up the control loop may lead to a compromise between a reasonably low output ripple and a pf still reasonably high; l poor transient response: as to this point too, speeding up the control loop may lead to a compromise between an acceptable transient response and a reasonablyhigh pf; + - multiplier v ref2 over-voltage detection voltage regulator uvlo internal supply 7v + - 2.5v r1 r2 r s q +- driver starter + - zero current detector disable 2.3v 1.8v v cc 8 1 23 4 zcd v cc inv comp mult cs gd 7 5 gnd 6 d97in547b 20v 40k 5pf figure 2. internal block diagram of the l6561. AN1059 application note 2/20
l large output capacitance (in the thousand m f, depending on the output power) is required: however, cheap standard capacitors and not costly high-quality parts are needed. in fact, a low esr and an adequate ac current capability are automatically achieved. besides, in conventional flyback convert- ers there is usually plenty of output capacitance too, thus this is not so dramatic as it may seem at first sight; l secondary post-regulation will be required where tight specifications on the output ripple and/or on the transient behaviour are given. however, this is true also for a standard flyback; l the system is unable to cope with line missing cycles at heavy load unless an exceedingly high output capacitance is used. in the following, the operation of a high-pf flyback converter will be discussed in details and numerous relationships, useful for its design, will be established. preliminary statements in order to generate the equations governing the operation of a high-pf flyback converter working in tm, refer also to the internal block diagram of the l6561(see fig. 2). for details concerning the operation of the l6561, please refer to ref. [1]. the following assumptions will be made: 1. the line voltage is perfectly sinusoidal and the rectifier bridge is ideal, thus the voltage downstream the bridge, sensed by the input of the l6561's multiplier (mult, pin 3) is a rectified sinusoid: v in (t) = v pk ? |sin (2 ? p ? f l ? t)| where v pk is equal to the rms line voltage, v rms , times the square root of 2, and f l is the line fre- quency (usually 50 or 60 hz). 2. the output of l6561's error amplifier (v comp ) is constant for a given line half-cycle; 3. transformer's efficiency is 1 and its windings are perfectly coupled. 4. zcd circuit's delay is negligible thus the converter works exactly on the boundary between continuous and discontinuous current conduction mode (tm operation). as a result of the first two assumptions, the peak primary current is enveloped by a rectified sinusoid: i pkp (t) = i pkp ? |sin (2 ? p ? f l ? t)| (1) one consequence of assumption 3 is that the peak secondary current is proportional to the primary one, depending on transformer's primary-to-secondary turns ratio n: i pks (t) = n ? i pkp (t) to simplify the notation, in the following the phase angle q =2 ? p ? f l ? t of the sinusoidal quantities will be indicated and all the quantities depending on the instantaneous line voltage will be considered as a function of q , instead of time. timing relationships the on-time of the power switch is expressed by: t on = l p ? i pkp (q) v in (q) = l p ? i pkp v pk (2), where l p is the inductance of transformer's primary winding. eqn. (2) shows that t on is constant over a line half-cycle, exactly like in boost topology. the off-time is instead variable: t off = l s ? i pks (q) ( v out + v f ) = l p n 2 ? n ? i pkp (q) ( v out + v f ) = l p ? i pkp ? |sin (q) | n ? ( v out + v f ) (3), AN1059 application note 3/20
where l s is the inductance of the secondary winding, i pks ( q ) the peak secondary current, v out the output voltage of the converter (supposed to be a regulated dc value) and v f the forward drop on the output catch diode. since the system works in tm, the sum of the on and the off times equals the switching period: t = t on + t off = l p ? i pkp v pk ? ? ? ? 1 + v pk v r ? |sin (q) | ? ? ? (4) where v r =n ? (v out +v f ) is the so-called reflected voltage. the switching frequency f sw =t -1 , therefore, varies with the instantaneous line voltage: f sw = v pk l p ? i pkp ? 1 1 + v pk v r ? |sin (q) | and reaches its minimum value on the peak of the sinusoid (sin ( q )=1): f sw min = v pk l p ? i pkp ? 1 1 + v pk v r (5) this value, calculated at the minimum line voltage, must be greater than the maximum one of the inter- nal starter of the l6561 ( 14 khz ), in order to ensure a correct tm operation. to accomplish with this requirement, the primary inductance l p will be properly selected (not exceeding an upper limit). actually, to minimise the size of the transformer, the minimum frequency will usually be selected quite higher than 15 khz, say 25-30 khz or more, so the value of l p needs not have a tight tolerance. the duty cycle, that is the ratio between the on-time and the switching period, will vary with the instan- taneous line voltage as well (because of the variation of t off ), as it is possible to find by dividing eqn.(2) by (4): d = t on t = 1 1 + v pk v r ? |sin (q) | (5') equations (2) and (4) show that t on and t, respectively, can be short at will if i pkp (i.e. the load) tends to zero, especially at high input voltage. in the real-world operation, it must be considered that t on cannot go below a minimum amount and so will do the switching period as well. this minimum (typically, 0.4- 0.5 m s) is imposed by the internal delay of the l6561 and by the turn-off delay of the mosfet. when this minimum is reached, the energy drawn each cycle exceeds the short-term demand from the load, thus the control loop causes some cycles to be skipped so as to maintain the long-term energy bal- ance. when the load is so low that many cycles need to be skipped, the amplitude of the drain voltage ringing becomes so small that it can no longer trigger the zcd block of the l6561. in that case the inter- nal starter of the ic will start a new switching cycles sequence. something similar applies to the duty cycle as well, which eqn. (5') predicts to be unity when q = 0, that is at the zero-crossings of the mains voltage. in reality, a number of parasitic effects cause t on and t off not to follow the ideal relationships (2) and (3). the effect of that on the overall operation is however negligible because the energy processed near a zero-crossing is very little. in the following, the ratio between the line peak voltage v pk and the reflected voltage v r will be indi- cated with k v : k v = v pk v r energetic relationships apart from the duty cycle, all the quantities expressed in the timing relationships depend on the through- put power, which is represented in the above equations by i pkp , the peak primary current occurring at AN1059 application note 4/20
the peak of the sinusoid of the primary voltage. the following relationships relate i pkp to the input power p in and allow both to explicate the timing rela- tionships and to calculate all the currents circulating in the circuit. the primary current i p (t) is triangular-shaped and flows only during the switch on-time, as illustrated by the shaded triangles shown in fig. 3. as earlier stated by equation (1), during each half-cycle the height of these triangles varies with the instantaneousline voltage: i pkp ( q )=i pkp ? |sin ( q )|, their width is constant but they are spaced out by a variable amount given by (3). looking at the primary on a of l o time scale, the current i in ( q ) downstream the bridge rectifier is the aver- age value of each triangle over a switching cycle (the thick black curve of fig. 3): i in (q) = 1 2 ? i pkp (q) ? d = 1 2 ? i pkp ? |sin (q) | 1 + k v ? |sin (q) | primary current peak envelope secondary current peak envelope average primary current on off switch figure 3. high-pf flyback current waveforms iin( q ) after the bridge kv=4 kv=2 kv=1 kv=0.5 0 1.57 3.14 4.71 6.28 0 0.25 0.5 0.75 1 q figure 4a. primary current (@ f l time scale) iin( q ) before the bridge kv=0.5 kv=1 kv=2 kv=4 0 1.57 3.14 4.71 6.28 1 0.5 0 0.5 1 q figure 4b. line current (@ f l time scale) AN1059 application note 5/20
this function, shown in fig. 4a for different values of k v , is a periodic even function, at twice line fre- quency, not negative because of the bridge rectifier. conversely, the current drawn from the mains will be the oodd counterparto of (6), at line frequency, as shown in fig. 4b). actually, it is realistic to think that a filtering action eliminates the switching frequency component of the current upstream the rectifier bridge, so that the mains ocan seeo only the average value. this current would be sinusoidal for k v = 0 but will be distorted from an ideal sinusoid so much as k v increases. since k v cannot be zero (which would require the reflected voltage to tend to infinity), flyback topology does not permit unity power factor even in the ideal case, unlike boost topology. in order to simplify the following calculations, it is possible to eliminate the absolute value from | sin ( q )| by considering q [0 , p ] and assuming the various functions to be either even or odd by definition, de- pending on their physical role. the input power p in will be calculated by averaging the product v in ( q ) ? i in ( q ) over a line half-cycle: p in = v in (q) ? i in (q) ____________ = 1 2 ? v pk ? i pkp ? sin 2 (q) 1 + k v ? sin (q) (7). it is now advantageousto introduce the following function: f2 ( x )= sin 2 (q) 1 + x ? sin (q) = 1 p ? o p sin 2 (q) 1 + x ? sin (q) d q (8), whose diagram as a function of the variable x is shown in fig. 5. although a closed form exists for the integral in (8), it is not so handy, thus for practical use it is more convenient to provide a obest fito approximation: f2 ( x ) 0.5 + 1.4 ? 10 - 3 ? x 1 + 0.815 ? x . from (7), taking (8) into account, it is possible to calculate i pkp : i pkp = 2 ? p in v pk ? f2 ( k v ) , which will assume its maximum value at minimum mains voltage. the total rms value of the primary current, useful for power loss estimate on the primary side, is calcu- lated considering the rms value of each triangle of i p (t) and averaging over a line half-cycle: i rmsp = ````````` ` 1 3 ? i pkp 2 (q) ? d = i pkp ? ```````` ` 1 3 ? sin 2 (q) 1 + k v ? sin (q) = i pkp ? ```` f2 ( k v ) 3 (9). the dc component of the primary current, useful to discriminate dc and ac losses in the transformer, is the average value of i in ( q ) over a line half-cycle: i dcp = i in (q) ____ _ = 1 2 ? i pkp ? sin (q) 1 + k v ? sin (q) (10). considering the following function: f1 ( x )= sin (q) 1 + x ? sin (q) = 1 p ? o p sin (q) 1 + x ? sin (q) d q , 0123456789 10 0 0.1 0.2 0.3 0.4 0.5 f2( ) x x figure 5. high-pf flyback characteristic functions: f2(x) diagram AN1059 application note 6/20
equation (10) can be rewritten as follows: i dcp = 1 2 ? i pkp ? f1 ( k v ) . also for f1(x) it is more practical to furnish a best fit approximation rather than the exact expression: f1 ( x ) 0.637 + 4.6 ? 10 - 3 ? x 1 + 0.729 ? x . as to the current on the secondary side, i s (t), it is the series of triangles complementary to the pri- mary's (the white ones in fig. 3). its twice line fre- quency representation will be again the average over a switching cycle: i o (q) = 1 2 ? i pks (q) ? ( 1 - d )= 1 2 ? i pks ? k v ? sin 2 (q) 1 + k v ? sin (q) (11). like the primary current (6), also (11) is a not negative periodic even function. according to assumption 3), i pks would equal n ? i pkp . to consider a more realistic case (the secondary peak current is slightly less than n ? i pkp because of transformer's losses and other non-idealities) it is possible to derive i pks from the dc value of the output current, iout, of the converter, which is one of the design data. by equalling the average value of (11) over one line half-cycle to i out , it is possible to find: i pks = 2 ? i out k v ? f2 ( k v ) . the total rms secondary current is calculated as follows: i rmss = ``````````` 1 3 ? i pks 2 (q) ? ( 1 - d ) _____________ _ = i pks ? ````````` k v 3 ? sin 3 (q) 1 + k v ? sin (q) (12) it will be now introduced the third characteristic function of the high-pf flyback: f3 ( x )= sin 3 (q) 1 + x ? sin (q) = 1 p ? 0 p sin 3 (q) 1 + x ? sin (q) d q 0.424 + 5.7 ? 10 - 4 ? x 1 + 0.862 ? x . with this definition, it is possible to express (12) as follows: i rmss = i pks ? `````` k v ? f3 ( k v ) 3 . for both primary and secondary side, the ac com- ponent of current can be calculated with the general relationship: i aci = ````````` i rmsi 2 - i dci 2 ( i = p,s ) . 012345678910 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 f1( ) x x figure 6. high-pf flyback characteristic functions: f1(x) diagram 012345678910 0 0.1 0.2 0.3 0.4 0.5 f3( ) x x figure 7. high-pf flyback characteristic functions: f3(x) diagram AN1059 application note 7/20
power factor and total harmonic distortion under the assumption of a sinusoidal line voltage, the power factor pf can be expressed as: pf = real input power apparent input power = v rms ? i rms1 v rms ? i rmsin = i rms1 i rmsin ( 13 ) where v rms is the (effective) line voltage, i rms1 is the effective value of the first harmonic (it will be in phase with the line voltage) and i rmsin the total effective value of the input current waveform (6). i rms1 can be simply calculated from the numerator of (13): i rms1 = p in v rms = ` ` 2 ? p in v pk ( 14 ) . it is worth noticing that i rmsin i rmsp . in fact (9) contains also the energy contribution due to the switch- ing frequency, while equation (13) - and therefore i rmsin too - refers only to line frequency quantities. i rmsin is the rms value of (6), which is by definition: i rmsin = ```` i in 2 (q) ____ _ = 1 2 ? i pkp ? ``````````` 1 p ? 0 p ? ? ? sin (q) 1 + k v ? sin (q) ? ? ? 2 d q( 15 ) . inserting (14) and (15) in (13) yields the theoretical expression of pf (note that it depends only on k v ). its diagram, depicted in fig. 8, shows how it keeps quite close to 1. for practical use, pf can be approxi- mated by: pf(k v ) 1 - 8.1 ? 10 -3 ? k v + 3.4 ? 10 -4 ? k v 2 (16) obviously numerous non-idealities, basically the ones mentioned in the section otiming relation- shipso, contribute to achieve a real-world pf lower than the theoretical value given by (16), especially at light load and high mains voltage. the total harmonic distortion (thd) of the line cur- rent is defined in percentage as: thd % = 100 ? ````` 2 i rmsn 2 i rms1 , where i rmsn is the rms amplitude of the n-th harmonic. still under the assumption of an ideally sinusoi- dal input voltage, the thd is related to the power factor by the following relationship: thd% = 100 ? ````` 1 pf 2 - 1. fig. 9 illustrates the dependence of thd% on kv. for a given reflected voltage, it shows how the total harmonic distortion degrades when the line voltage builds up. transformer the design of the transformer is a complex proce- dure that involves several steps: selecting the core material and geometry, determining the maximum peak magnetic flux density (and whether this is lim- kv pf(kv) 0123 456 78910 0.95 0.96 0.97 0.98 0.99 1 figure 8. theoretical power factor of high-pf flyback converters thd% (kv) kv 0123 456 78910 0 8 16 24 32 40 figure 9. thd% as a function of kv AN1059 application note 8/20
ited by core saturation or losses), determining the core size, defining the primary and secondary wind- ings (turns number and wire gauge) as well as calculating the air-gap necessary to achieve the desired inductance. moreover, additional considerations concerning the assembly are needed for meeting safety requirements, maximising magnetic coupling and minimising parasitic high frequency effects, not to mention the constraints imposed by the specific application, if any. some parameters are needed to start the design of the transformer. the (maximum) primary inductance will be calculated by solving (5) for l p : l p 1 2 ? f2 ( k vmin ) 1 + k vmin ? v pkmin 2 f swmin ? p inmax , or by simply looking up the diagram of fig. 10, where the primary inductance required for 1w input power is plotted against f swmin , for different values of k vmin and for the two typical mains voltage ranges. the value taken from fig. 10 (in mh), will be divided by the maximum input power to get the actual primary in- ductance required by the specific application. the primary-to-secondary turns ratio will be given by: n = v r v out + v f . with the peak and rms current values calculated in the oenergetic relationshipso section, the design can be carried out just like for any conventional flyback transformer, thus no particular procedure will be con- sidered. anyway, as a design aid to core selection, two expressions for determining the minimum required core area-product (winding window area times effective magnetic cross section) will be provided: ap min = ? ? ? 460 ? p in f swmin ? ( 1 + k v ) ? `````` ` f2 ( k v ) ? ? ? 1.316 ( 17 ) ; ap min = ? ? ? 480 ? p in f swmin ? ( 1 + k v ) ? `````` ` f2 ( k v ) ? ? ? 1.585 ? [j h ( k v ) ? f swmin + j e ( k v ) ? f swmin 2 ] 0.66 ( 18 ) ; . 210 4 310 4 410 4 510 4 610 4 5 25 45 65 85 l( ) , 0.5 fmin l( ) , 1 fmin l( ) , 1.5 fmin l( ) , 2 fmin l( ) , 2.5 fmin fmin 210 4 310 4 410 4 510 4 610 4 0 100 200 300 400 l( ) , 0.5 fmin l( ) , 1 fmin l( ) , 1.5 fmin l( ) , 2 fmin l( ) , 2.5 fmin fmin lmax [mhw] lmax [mhw] fswmin [hz] fswmin [hz] 110vac or wide-range mains 220vac mains k vmin = 0.5 1 1.5 2 2.5 k vmin = 0.5 1 1.5 2 2.5 figure 10. maximum specific primary inductance required AN1059 application note 9/20
where j h (kv) and j e (kv) are functions related to hysteresis and eddy current losses, whose best fit ap- proximation are respectively: j h ( k v ) 1.87 + 1.26 ? k v 1 + 0.55 ? k v ? 10 - 5 j e ( k v ) 1.88 + 1.06 ? k v 1 + 0.34 ? k v ? 10 - 10 . formula (17) assumes that the maximum peak flux density inside the core is limited by core saturation and that all transformer losses are located in the windings; (18) assumes that core losses limit the flux swing and the total dissipation are half due to core losses and half to windings losses. common to both formulae are the following assumptions: 1. the material is a typical power ferrite (3c85 from philips, n67 from siemens or similar grades) with a saturation flux density above 0.3 tesla; 2. the windings occupy 40% of the total window area to leave space for isolation lay- ers, creepage and clearance distances; 3. primary and secondary winding wires are proportioned for equal rms current den- sity; 4. core and/or copper losses result in 30 c hot spot temperature rise (no forced cooling); 5. skin and proximity effects are neglected, considering the frequency range involved. for a given f swmin , one should try both formu- lae (considering k v at minimum line voltage) and use the higher resulting value. core losses become dominant for core selection above 45 khz at this power level. in fig. 11, the higher value resulting from (17) and (18) is plotted against f swmin for different values of k v , considering 30w output power with an estimate of 85% efficiency. clamp network the overvoltage spikes due to the leakage inductance of the trans- former are usually limited by an rcd clamp network, as illustrated in fig. 12a. it can be advantageous the use of a zener (or transil) clamp (see fig. 12b) when minimisation of power losses at light load is de- sired. considering the rcd clamp, the capacitor is selected so as to have an assigned overvoltage d v (as a rule of thumb, half the reflected voltage) at turn-off such that the voltage rating of the mosfet is never ex- ceeded. from energetic balance, it is possible to write: c min = l lk ? i pkpmax 2 d v ? (d v + 2 ? v r ) , where l lk is the leakage inductance, which can be estimated in the range of 1 to 3% of the primary inductance if the transformer is properly manufactured, and: i pkpmax = 2 ? p inmax v pkmin ? f2 ( k vmin ) the capacitor undergoes large current spikes and therefore it should be a very low esr type with polypropylene or polystyrene film dielec- tric. 210 4 2.5 10 4 310 4 3.5 10 4 410 4 4.5 10 4 510 4 5.5 10 4 610 4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 v( ) , fmin 0.5 v( ) , fmin 1 v( ) , fmin 1.5 v( ) , fmin 2 v( ) , fmin 2.5 fmin kv= 0.5 kv= 1 kv= 1.5 kv= 2.5 kv= 2 fswmin[hz] ap[cm ] 4 figure 11. minimum transformer ap required for a 30w application. r c d figure 12a. rcd clamp. d t figure 12b. zener (transil) clamp. AN1059 application note 10/20
the minimum resistor value can be found by imposing that the voltage on the capacitor at the beginning of each switching cycle never falls below the reflected voltage : r min = 1 f swmin ? c ? ln ? ? ? 1 + d v v r ? ? ? the power rating of this resistor can be estimated by considering the dc dissipation due to the reflected voltage and the leakage inductance energy: p r = v r 2 r + 1 2 ? ( 1 + k vmin ) ? f2 ( k vmin ) ? l lk ? i pkpmax 2 ? f swmin . the blocking diode will be not only a very fast recovery type but will also feature a very fast turn-on time. in fact, the instantaneous forward drop at turn-on generates a spike, exceeding the overvoltage d v, that must be small. the diode will be rated for repetitive peak currents equal to i pkp , and with a breakdown voltage greater than v pkmax +v r . considering a zener or a transil, its clamping voltage can be approximated with its breakdown voltage. in fact, the peak current is quite small and it is possible to neglect the contribution due to the dynamic resis- tance. the breakdown voltage, which should account for the drift due to the temperature rise, will then be: v (br) v cl =v r + d v. the steady-state power dissipation capability must be at least: p transil = v ( br ) 2 ? ( v ( br ) - v r ) ? ( 1 + k vmin ) ? f2 ( k vmin ) ? l lk ? i pkpmax 2 ? f swmin, while there is no concern about its peak power dissipation, since this is defined for power pulses of 1 ms (leakage inductance is typically demagnetized in less than 1 m s). as to the blocking diode, what said earlier about the one of the rcd clamp still applies. output capacitor the output capacitor undergoes the ac component of the secondary current i s (t), (see fig 3). besides, to achieve a reasonably high pf, the voltage control loop is slow (typically, its bandwidth is be- low 100 hz). as a result, there is a quite large voltage ripple appearing across the output capacitor. this ripple has two components. one is related to the high frequency triangles and depends almost entirely on the esr of the output ca- pacitor, being the capacitive contribution practically negligible. its maximum amplitude, occurring on the peak of the sinusoid, will be: d v o ( hf ) = i pks esr . the second component of the ripple is related to the twice line frequency envelope and, unlike the high frequency component, depends on the capacitance value, while the esr contribution can be neglected. to calculate the amplitude of this component, only the fundamental harmonic of (11), at twice line fre- quency, will be taken into account. in fact, the amplitude of the higher order (even) harmonics is much smaller and the impedance of the capacitor decreases with frequency as well. according to fourier's analysis, the (peak) amplitude of the fundamental harmonic of (11) is: i o2 = i pks ? k v p ? 0 p sin 2 (q) ? cos ( 2 ? q) 1 + k v ? sin (q) d q , that, defining the following function: AN1059 application note 11/20
h2 ( x )= 1 p ? ? ? ? 0 p sin 2 (q) ? cos ( 2 ? q) 1 + x ? sin (q) ? ? ? d q 0.25 - 1.5 ? 10 - 3 ? x 1 + 1.074 ? x ( 19 ) , can be expressed as: i o2 = i pks ? k v ? h2 ( k v )= 2 ? i out ? h2 ( k v ) f2 ( k v ) . the absolute value in (19) is needed since the integral results negative, because the harmonic is 180 out of phase. finally, the peak-to-peak amplitude of the low frequency output ripple is: d v o = 2 ? i o2 z ( 2fl ) ( c o ) = 1 p ? h2 ( k v ) f2 ( k v ) ? i out f l ? c o . in most cases, once a capacitor is selected so as to meet the requirement on the low frequency ripple, the esr will be low enough to make the high frequency ripple negligible. multiplier bias and sense resistor selection a resistor divider feeds a portion of the input voltage into pin 3 (mult) to build the sinusoidal reference for the peak primary current. to set properly the operating point of the multiplier the following procedure is recommended. first, the maximum peak value for v mult ,v multpkmax , is selected. this value, which will occur at maxi- mum mains voltage, should be 2.5 to 3v in wide range mains applications and 1 to 1.5v in case of single mains. the minimum peak value, occurring at minimum mains voltage will be: v multpkmin = v multpkmax ? v pkmin v pkmax this value, multiplied by the minimum guaranteed d v cs / d v comp will give the maximum peak output volt- age of the multiplier: v cxpk = 1.65 ? v multpkmin if the resulting v cxpk exceeds the linearity limit of the current sense (1.6 v), the calculation should be re- peated beginning with a lower v multpkmax value. in this way, the divider ratio will be: k p = v multpkmax v pkmax and the individual resistor values can be chosen by setting the current through them, in the hundreds m a or less, to minimise power dissipation. the value of the sense resistor, connected between the source of the mosfet and ground, across which the l6561 reads the primary current, is calculated as follows: r s v cxpk i pkpmax . the resistor will be rated for a power dissipation equal to: p s = r s ? i pkpmax 2 ? f2 ( k vmin ) 3 AN1059 application note 12/20
closing the control loop the control loop of a high-pf flyback converter based on the l6561, can be synthesised as in the block diagram of fig. 13. unlike conventional converters, in such regulators the control loop will have quite a narrow bandwidth so as to maintain v comp fairly constant over a given line cycle, as assumed at the beginning. this will en- sure a high pf. on the other hand, it is not possible to achieve a very high pf (>0.99), thus it makes no sense to have a very narrow bandwidth (<20 hz) like in boost pfc preregulators. this would degrade the transient response to line and load changes without any benefit. a compromise will then be found between these two contrasting terms. to the aim of deriving the transfer functions of the blocks in fig. 13, the narrow bandwidth of the control loop allows to assume that the control action takes place on the peak amplitude of the various quantities. the error amplifier (e/a) of the l6561 is compensated as illustrated in fig. 14. the transfer function g1(s) will be then: g1 ( s )= d v comp d v e =- r 7 r 6 ? 1 + s ? ( c 2 ? r 8 ) 1 + s ? [c 2 ? ( r 7 + r 8 ) ] . error amplifier multiplier power stage feedback + - g1(s) g2(s) g4(s) h(s) vref vout vcomp pwm modulator g3(s) i pk p + - vin zcd vcx ve figure 13. block diagram of the control loop of an l6561 - based high-pf flyback. comp inv 2.5v e/a + _ l6561 c2 r7 r6 to multiplier r8 figure 14. compensation of the error amplifier. AN1059 application note 13/20
the pole is placed at a very low frequency so that the gain at twice line frequency is quite less than unity, while the zero boosts the phase in the neighbourhood of the open-loop crossover frequency so as to provide phase margin. a variation d v comp , due to a line and/or load change, modifies the amplitude v cx of the rectified sinusoid at the output of the multiplier. this considering, the transfer function of the multiplier block will be: g2 = d v cx d v comp = k m ? k p ? v pk where k m is the gain of the multiplier (= 0.75 max.). the gain of the pwm modulator, which includes the current loop, is simply: g3 = d i pkp d v cx = 1 r s where r s is the sense resistor. small-signal analysis shows that the gain g4(s) of the power stage is: g4 ( s )= d v out d i pkp = n ? k v ? f2 ( k v ) g( k v ) + 1 ? r o 2 ? 1 + s ? ( c o ? esr ) 1 + s ? ( c o ? r o g( k v ) + 1 ) , where the function g (x) is defined as follows: g( x )= 1 + x f2 ( x ) ? df2 ( x ) dx 1 + 0.01 ? x 1 + 0.8 ? x . the feedback network can have different configurations, depending on the requirements on the toler- ance and on the regulation of the output voltage. in this context a popular configuration (see fig. 15) will be taken into consideration. it uses an optocou- pler for galvanic isolation between primary and secondary and a tl431, a cheap voltage reference/op- amp housed in a three pin package. the gain, h(s), at twice line frequency must be low. in fact, being the output voltage ripple quite high, a high gain could saturate the dynamics of the tl431 and/or of the optocoupler, besides complicating things in getting a narrow overall bandwidth. referring to fig. 15, it is possible to write: h ( s )= d v e d v out = 1 r 4 ? r 5 ? r 6 r 5 + r 6 ? ctr ? 1 + s ? c 1 ? ( r 1 + r 3 ) s ? ( c 1 ? r 1 ) , where ctr is the current transfer ratio of the optocoupler. when designing the control loop, first select the operating current of optocoupler's transistor (i c ). it is ad- vantageous to selects a low i c value (e.g. 1 ma): this will not only extend the lifetime of the device but, in the present case, will also help keep low the gain of the feedback network at twice line frequency. since in closed-loop operation the quiescent value of v e will be in the neighbourhood of 2.5v (internal reference of the l6561 e/a), r 5 will be: r 5 = 2.5 i c . r 4 will be selected so as to maintain v k voltage above 2.5v for a correct functionality of the tl431 even in the worst case, that is when the optocoupler exhibits its minimum ctr, because of the statistical spread of this parameter. AN1059 application note 14/20
therefore: r 4 < v out - 1 - 2.5 2.5 ? ctr min ? r 5 , where 1v is the typical drop across optocoupler's photodiode. keep r 4 close to the maximum for a low gain. r 1 and r 2 are selected to get the desired output voltage: r 2 = 2.5 i r2 ;r 1 = v out - 2.5 2.5 ? r 2 where 2.5 is the internal reference of the tl431 and i r2 the current flowing through r 2 . to have a low gain at twice line frequency, the zero of h(s) will be placed below 100hz and r 3 will be 4- 5 times less than r 1 . this yields the value of c 1 . the value of r 6 will be such that the twice mains frequency ripple superimposed on the static v e cannot trip the dynamic overvoltage protection of the l6561 (40 m a entering pin comp). approximately: r 6 > r 5 + r 5 r 4 ? ctr max ? d v o 40 ? 10 - 6 r 7 will be selected so as to allow the output of the error amplifier to swing all the dynamics. finally, r 8 and c 2 will be adjusted so that the crossover frequency of the open-loop gain is a good compromise be- tween a high enough pf and an acceptable transient response, ensuring also sufficient phase margin. the optional capacitor (in the m f range) connected in parallel to r 1 acts as a soft-start circuit that pre- vents overvoltages of the output at start-up, especially at light load. the two diodes decouple the capaci- tor during steady-state operation so that it does not interfere with the loop gain and provide a discharge path when the converter is turned off. vout r4 r1 r3 r2 tl431 c1 1 m f c2 l6561 comp inv vcc r5 r6 r7 v k i f i c v e r8 figure 15. feedback network and connection to the error amplifier. AN1059 application note 15/20
calculation example an example of step-by-step design procedure of an l6561-based, high-pf flyback converter will be here described for reference. it concerns a 30w ac adapter for portable equipment. the application was ac- tually realised and some experimental results are here presented. 1. design specifications: - mains voltage range: v acmin = 88 vac, v acmax = 264 vac - minimum mains frequency: f l =50hz - dc output voltage: v out =15v - maximum output current: i out =2a - maximum 2f l output ripple: d v o = 1v peak-to-peak 2. pre-design choices: - minimum switching frequency: f swmin = 25 khz - reflected voltage: v r = 100v - leakage inductance overvoltage: d v =70v - expected efficiency: h = 85% 3. preliminary calculations: - minimum input peak voltage: v pkmin = v acmin ? ` ` 2 = 88 ? `` 2 - 4 = 120v (4v total drop on r ds(on) , rs, ...) - maximum input peak voltage: v pkmin = v acmin ? ` ` 2 = 264 ? ` ` 2 = 373v - maximum output power: p out =v out ? i out =15 ? 2 = 30w - maximum input power: p in = p out h ? 100 = 30 85 ? 100 = 35.3w - peak-to-reflected voltage ratio: k v = v pkmin v r = 120 100 = 1.2 - characteristic functions value: f1(1.2)=0.343; f2(1.2)=0.254; f3(1.2)=0.209; f5(1.2)=0.108 4. operating conditions: - peak primary current: i pkp = 2 ? p in v pkmin ? f2 ( k v ) = 2 ? 35.3 120 ? 0.254 = 2.32a - rms primary current: i rmsp = i pkp ? ```` f2 ( k v ) 3 = 2.32 ? ```` 0.254 3 = 0.675a - peak secondary current: i pks = 2 ? i out k v ? f2 ( k v ) = 2 ? 2 1.2 ? 0.254 = 13.1a - rms secondarycurrent: i rmss = i pks ? `````` k v ? f3 ( k v ) 3 = 13.1 ? ``````` 1.2 ? 0.209 3 = 3.79a 5. transformer: - primary inductance: l p = v pkmin ( 1 + k v ) ? f swmin ? i pkp = 120 ( 1 + 1.2 ) ? 25 ? 10 3 ? 2.32 = 940 m h - primary-to-secondary turns ratio: n = v r ( v out + v f ) = 100 15 + 0.6 = 6.41 from diagram of fig. 11, by interpolation, the minimum ap required is about 0.5 cm 4 .an etd29 core (ap = 0.684 cm 4 ), 3c85 grade is selected. from the relevant datasheet, with 1 AN1059 application note 16/20
mm air gap 90 primary turns will result in about 970 m h primary inductance. 14 secondary turns give a 6.43 turns ratio, very close to the target. estimating the thermal resistance of the etd29 equal to 26 c/w, the maximum power dissipation (supposed to be on copper only) for 30 c hot-spot temperature rise will be 1.15w (half will be allocated to the primary and half to the secondary). this requires the resistance of the primary to be no more than 1.26 w and the secondary's no more than 40 m w . an awg27 ( ? 0.4 mm) wire for the primary and a strand of 5xawg27 for the secondary will meet the requirement.the primary winding will be split in two halves of 45 turns each, series connected, and the secondary will be sandwiched in be- tween to reduce leakage inductance. 6. mosfet selection - maximum drain voltage:v dsmax =v pkmax +v r + d v = 373 + 100 + 70 = 543v there is margin to select a 600 v device. this will minimise gate drive and capacitive losses. assuming that the mosfet will dissipate 5% of the input power, that losses are due to con- duction only, and that r ds(on) doubles at working temperature, the r ds(on) at 25 c should be about 2 w . an stp4na60 (r ds(on) = 2.2 w max.) is selected. 7. catch diode selection - maximum reverse voltage: v revmax = v pkmax n + v out = 373 6.41 + 15 = 73.2v a 100v schottky diode will minimise conduction losses. as to its current rating, a tentative value can be 40% of the peak current: i f = 0.4 ? i pks = 0.4 ? 13.1 = 5.2a. a suitable device could be the stps8h100d. from the relevant datasheet, the power dissipation is estimated as: p diode = 0.48 ? i out + 0.013 ? i rmss 2 = 0.55 ? 2 + 0.013 ? 3.79 2 = 1.15w, which is acceptable. 8. output capacitor selection the minimum capacitance value that meets the specification on the 100/120 hz ripple is: c outmin = 1 p ? f l ? h2 ( k v ) f2 ( k v ) ? i out d v o = 0.108 ? 2 3.14 ? 50 ? 0.254 ? 1 = 5417 m f three 2200 m f electrolytic capacitors will have an esr low enough to consider the high fre- quency ripple negligible as well as sufficient ac current capability. 9. clamp network with a proper construction technique, the leakage inductance can be reduced to as much as 2% of the primary inductance, that is 20 m h in the present case. a transil clamp is selected. the clamp voltage will be v cl =v r + d v = 100 + 70 = 170v. the steady-state power dissipa- tion is estimated to be about 2w. a p6ke170a transil is selected. the blocking diode is an stta106. 10. multiplier bias and sense resistor selection assuming a peak value of 2.4v (@v ac = 264v) on the multiplier input (mult, pin 3), the peak value at minimum line voltage will be v multpkmin = 2.4 ? 88/264 = 0.8v which, multiplied by the maximum slope of the multiplier, 1.65, gives 1.32v peak voltage on current sense (cs, pin 4). since the linearity limit (1.6v) is not exceeded, this is acceptable. the divider ratio will then be 2.4/( `` 2 ? 264) = 6.43 ? 10 -3 . considering 120 m a current for the divider, the lower resistor will be 20k w , and the upper one 3m w .the sense resistor will not exceed 1.32/2.32 = 0.57 w (0.5 w is selected), while its power rating will be 0.5 ? i rmsp 2 = 0.5 ? 0.675 2 = 228mw 11. feedback and control loop the selected optocoupler is a 4n35 from toshiba. 1 ma quiescent collector current is se- lected. from opto's datasheet, with 1ma collector current, the diode current can be between 1 and 2 ma approximately (0.5 < ctr < 1). AN1059 application note 17/20
an emitter resistor of 2.4k w , will give the desired collector current, thus the bias resistor should satisfy the inequality r 4 < 15 - 1.2 - 2.5 2.5 ? 0.5 ? 2.4 = 5.4k w . select r 4 = 5.1k w . as to the output divider, with r 2 = 2.4k w , the upper resistor will be r 1 = 12k w . select r 3 = 2.2 k w . with c 1 =1 m f the zero will be at about 70 hz, which is acceptable. r 6 should be so that r 6 > 2.4 ? 10 3 + 2.4 5.1 ? 1 ? 1 40 ? 10 - 6 = 14k w . select r 6 =20k w . by selecting r 7 =39k w ,r 7 = 9.1 k w and c 2 = 220 nf, the open-loop crossover frequency and phase mar- gin will be 50 hz and 42 respectively. the complete electrical schematic of this application is illustrated in fig.16, fig. 17 presents some results of its bench evaluation and fig. 18 shows some significant waveforms. 2 1 l6561 4 7 3 5 6 8 88 to 264 vac 15 vdc / 2a 470 nf 3m w 470 k w p6ke170a stta106 47 m f 47 k w 10 w 0.5 w 20 k w 2.4 k w 20 k w 5.1 k w 12 k w 2.2 k w 2.4 k w tl431 4n35 4n35 2.2 nf 220 nf stp4na60 stps8h100d 3x2200 m f 1 m f 1n4148 2a fuse 4.7 nf 2.2 m f 1n4148 1n4148 39 k w transformer specs: core: etd29, 3c85 grade or equivalent 1 mm airgap for 1 mh primary inductance. n1: 2 series windings, 45 t each, awg27 ( ? 0.41 mm) n2: 14 t,5xawg27 n3: 14t, awg32 ( ? 0.24 mm). disable 9.1 k w n1 n2 n3 df06m figure 16. 30w high-pf flyback with the l6561: electrical schematic figure 17. 30w high-pf flyback with the l6561: evaluation results iout = 0.5a iout = 2a iout = 1a iout = 0.1a 120 180 240 50 60 70 80 90 100 mains voltage [vac] efficiency [%] 120 180 240 0.6 0.7 0.8 0.9 1 mains voltage [vac] power factor iout = 0.1a iout = 0.5a iout = 1a iout = 2a 120 180 240 0.9 1 1.1 1.2 1.3 1.4 mains voltage [vac] input power [w] pout = 500 mw AN1059 application note 18/20
references [1] ol6561, enhanced transition mode power factor correctoro, (an966) [2] oflyback converters with the l6561 pfc controllero, (an1060) figure 18. 30w high-pf flyback with the l6561: principal waveforms v in =90v ac ,p out = 30w left : peak primary current envelope right, upper trace: mains current right, lower trace: low-frequency primary current AN1059 application note 19/20
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com AN1059 application note 20/20

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